As I sent to rasterlist a earlier
today:
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Anyone used these together? There appears to
be some odd bank switching to the ram and I can't quite get a handle on
it. Have a board that watch dogs constantly.
As far as I can see there is something wrong in the
DRAM address selector. Pin 8 of the LS10 @ E3 never changes. I piggy
backed another chip on it with pin 8 pulled up and it also gave the same
result. As far as I can see all the inputs to that area are correct but I
am wondering about ~IRQH which is the hardware interrupt signal. There is
a note on the schematics that this signal will disable the DRAM address
controller from setting the MADSEL.
Tracking ~IRQH back to its source it appears that
16FLIP is triggering which leads me to FLIP which is triggering. Now I
wouldn't expect FLIP to fire unless I had the cocktail strap in. Plus I am
running -01 roms which don't even support FLIP.
As you can probably guess I am going in circles
just a bit.
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A bit more information, going over the sync section of the schematics I
noticed something odd, the HBLANK and 128H signals are both the same count
15.6hz. I would have thought that the HBLANK should be 1/2 the rate of
128H as it is one step further down the counter.
And going back to FLIP, looking at the xxxV signal generation the sourcing
clock for this section appears to be FLIP. Now I am really confused.
Ideas?
David